This invention relates in general to systems employing multiple clock signals and in particular, to a method and circuit for selectably switching between a plurality of clock signals available in a system to provide a selected clock signal to a circuit in the system while minimizing the occurrence of transients such as glitches during the switching process.
A circuit for selectably switching between multiple clock signals has a number of practical applications. For example, where multiple memory devices operate at different speeds in a computer system, a circuit for selectably switching between multiple clock signals is useful in conjunction with a memory controller for controlling the reading and writing of data from and to the multiple memory devices. As another example, where a power saving circuit detects an idle condition or a power down request in a system, a circuit for selectably switching between multiple clock signals is useful in conjunction with the power saving circuit for switching from a normal operation mode clock signal to a slower, idle mode or power saving clock signal as the system clock signal.
FIG. 1a illustrates a conventional multiplexer 10 ("MUX") which may perform such selectable switching function, and FIG. 1b illustrates timing diagrams relating to the operation of the MUX 10. The MUX 10 receives at its inputs, first and second clock signals, CLK1' and CLK2', and passes, as determined by the state of a select signal CLK.sub.-- SEL' received at its select input, one or the other input clock signal, CLK1' or CLK2', as a current clock signal, CUR.sub.-- CLK', at its output. For example, when the state of the select signal CLK.sub.-- SEL' is HIGH, the MUX 10 passes the first clock signal CLK1' to its output as the current clock signal, CUR.sub.-- CLK', and when the state of the select signal CLK.sub.-- SEL' is LOW, the MUX 10 passes the second clock signal CLK2' to its output as the current clock signal, CUR.sub.-- CLK'.
One problem with using the MUX 10 for selectably switching between multiple clock signals, is that objectionable transients in the form of glitches, for example, may occur during the switching process. Referring to FIG. 1b, with the timing conditions depicted therein, an effective time period, teff, occurs as the result of the select signal CLK.sub.-- SEL' changing state at time t2. This effective time period, teff, is significantly less than a time period, tclk1, for the first clock signal CLK1' being passed prior to time t2, and significantly less than a time period, tclk2, for the second clock signal CLK2' being passed after time t2. Consequently, the very short effective time period, teff, occurring at the time of switching the clock signals, CLK1' to CLK2' at time t2, causes a corresponding high frequency glitch to occur at that time, which may adversely affect the proper operation of the system.